Field of the Invention
The present invention relates to a pattern classifying technique.
Description of the Related Art
Techniques for classifying a specific pattern such as the human body or face in an image have been proposed. In particular, attention has recently been given to high-speed and low-cost pattern classification techniques for use in an integrated system such as a mobile terminal or an on-board device.
An algorithm for speeding up pattern detection has been proposed by P. Viola, M. Jones in Rapid Object Detection using a Boosted Cascade of Simple Features, Proceedings of IEEE Conference on Computer Vision and Pattern Recognition, Vol. 1, pp. 511 to 518, December 2001 (hereinafter referred to as Non-Patent Document 1). In this algorithm, parameters are generated by boosting learning, and weak classifiers are sequentially processed by using feature images. Then, it is determined, based on the result of classification performed by a weak classifier, whether to process the next weak classifier. If it is determined that the next weak classifier is not to be processed, the processing of the remaining weak classifiers is omitted.
According to Integral Channel Features, by Piotr Dollár, et al., Proceedings of British Machine Vision Conference, pp. 91.1 to 91.11, September 2009, the accuracy of pattern detection is improved by extending the technique of Non-Patent Document 1 and increasing the number of types of feature images.
A hardware implementation method for speeding up face detection has been proposed by Junguk Cho, et al. in Hardware Acceleration of Multi-View Face Detection, Proceedings of IEEE Symposium on Application Specific Processors, pp. 66 to 69, July 2009. The technique disclosed in Hardware Acceleration of Multi-View Face Detection, by Junguk Cho, et al., Proceedings of IEEE Symposium on Application Specific Processors, pp. 66 to 69, July 2009 reduces the processing time by processing weak classifiers for classifying the faces in a plurality of categories (postures and the like) in a spatially parallel manner and reading feature images from image window buffers.
The classification processing techniques that use a plurality of cascaded weak classifiers in order to implement highly accurate pattern classification, as disclosed in: Rapid Object Detection using a Boosted Cascade of Simple Features, by P. Viola, M. Jones, Proceedings of IEEE Conference on Computer Vision and Pattern Recognition, Vol. 1, pp. 511 to 518, December 2001; Integral Channel Features, by Piotr Dollar, et al., Proceedings of British Machine Vision Conference, pp. 91.1 to 91.11, September 2009; and Hardware Acceleration of Multi-View Face Detection, by Junguk Cho, et al., Proceedings of IEEE Symposium on Application Specific Processors, pp. 66 to 69, July 2009, are techniques commonly used as high-speed and low-cost techniques. Also, the type of feature image is a factor that affects the processing speed and accuracy of classification processing. The performance of classification processing can be improved by increasing the number of types of feature images, but the number of memories for holding feature images also increases.
Also, in order to reduce the reference time for referencing feature images and speed up weak classifier processing, in the technique disclosed in Hardware Acceleration of Multi-View Face Detection, by Junguk Cho, et al., Proceedings of IEEE Symposium on Application Specific Processors, pp. 66 to 69, July 2009, registers for holding feature images are provided. Feature images are referenced in parallel from the registers, and at the same time, a plurality of weak classifiers are processed. However, the use of registers as data holding devices is problematic in that the circuit scale is large. This problem becomes more prominent when the number of feature images is increased for the purpose of improving performance (Integral Channel Features, by Piotr Dollár, et al., Proceedings of British Machine Vision Conference, pp. 91.1 to 91.11, September 2009).